QC Design

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Plaquette v2025.1 released with major upgrades for circuit customization

We are thrilled to unveil Plaquette v2025.1, bringing a major leap in simulating hardware-tailored quantum error correction. This release introduces enhanced customizability for Plaquette’s circuit generator, enabling the design of fault-tolerant architectures that precisely match your hardware’s native gates, measurement strategies, and gate scheduling. Here is an overview of our latest:

  • Hardware-native gates for tailored circuit compilation. Different quantum technologies have distinct “native” gates, e.g. CZ for superconducting qubits and neutral atoms, Mølmer-Sørensen for trapped ions, etc. Plaquette v2025.1 now supports native CX or CZ gates out of the box, so you can generate QECC circuits that use only CX or only CZ gates based on your hardware’s preferred gate set.

  • Parallel gates and concurrent measurements. Platforms like superconducting qubits, neutral atoms, and trapped ions often allow multiple gates and measurements to be performed simultaneously. By introducing the new concurrent measurements, you will be able to measure multiple stabilizer elements in the same timestep. At the same time, the possibility to automatically parallelize two-qubit gates within the same concurrent measurement using a greedy algorithm will help you reduce idle times, minimize gate overhead, and design circuits with the best  logical error rates.

  • Gate scheduling for optimized error mitigation. The order in which two-qubit gates are performed, often called gate scheduling, has a profound impact on logical error rates. With Plaquette v2025.1, you can leverage the optimal schedules we provide for the planar code and its variants, or define your own schedules for emerging QEC codes to further optimize your fault-tolerance architectures.

As an example, let’s consider the effect of different gate schedules for the distance-7 rotated planar code. In the following plot, you can observe how naïve (“Ascending”) or randomized (“Randomized”) gate schedules lead to higher logical error rates than the optimal gate schedule (“No hook") which reduces the effect of hook errors.

Get in touch if you’d like to learn more about these features or request additional gate integrations!